1. Field of the Invention
The present invention generally relates to integrated circuits and, more particularly, to a method for laying-out designs of large scale and very large scale integrated circuits.
2. State of the Art
Integrated circuit modules can either be custom designed or can be designed by using a module generation technique such as a slice composition model. Although custom designs of integrated circuits often result in highly efficient use of silicon substrates, such designs are costly and time-consuming in terms of engineering.
In the art of designing integrated circuits, it is known that the slice composition method is particularly useful for laying out designs of integrated circuits which repeatedly use similar or identical circuit modules. Some examples of integrated circuits which are often designed by the slice composition technique are read only memories (ROM's), random access memories (RAM's), and programmable logic arrays (PLA's), and their use in application specific integrated circuits (ASIC's).
In the slice composition technique, frequently-used elements, or "cells," are often referred to as "tiles" or "leaves". The modular component cells are known as tiles because, by analogy to mosaic patterns formed of ceramic tiles, they can be placed adjacent to one another to form larger patterns. The modular cells are also known as leafs because, by analogy to the leafs of a tree, they form the lowest component in a hierarchy. For present purposes, patterns formed of modular cells will be called "blocks". And it should be understood that a block composed of a group of cells may be used as a module in a larger block.) Since individual types of cells are often used repetitively in a circuit design, the particular occurrence of a cell is called an "instance".
In conventional procedural layout methods, the spatial orientation of each cell must be designated by its specific cartesian coordinates. That is, conventional procedural layout methods require a detailed specification of the spatial orientation of cells. According to such conventional methods, once cells are positioned, they are interconnected. Thus, one drawback of such methods is that misplacements of cells or their routing lines can result in faulty operation of the resulting integrated circuit, even though the misplacements are barely perceptible to a circuit design engineer.
Typically, different types of modular cells are not uniform in size and therefore, do not fit together without some spatial adjustments. That is, when different types of cells are compiled to form a block, the ports of the cells will usually not be in alignment nor will the sides of the cells uniformly abut. To overcome this latter difficulty, it is known to employ a technique, known as composition wherein cells are stretchable; that is, according to this technique the size of the cells is expanded or shrunk as required to fill the area of interest in an integrated circuit. The main drawback of such methods is that they do not efficiently utilize space on a silicon substrate.